With the scaling down of device dimensions, design methodologies that take into account the compatibility of a semiconductor chip design with the capabilities of manufacturing technologies that will be employed in the actual chip fabrication have become increasingly important. The disconnect between design and manufacturing often occurs at the physical layout design level where a circuit is converted from a schematic level to actual shapes that are used in the manufacture of masks for lithographic patterning.
In view of the above, design methodologies need to include robust physical design verification methods that are effective in detecting potentially yield impacting design elements. A known design verification technique involves checking whether the dimensions of design elements are within predefined limits of width, length, diameter and other geometrical dimensions. However, such verification techniques are not very efficient in detecting certain types of problematic layout pattern such as yield detractors caused by spatial relationship between design elements and abnormalities in the field area. In view of the above, design verification techniques that are more efficient in detecting potentially problematic layout are desired.